The embodiment of the invention relates generally to reducing power grid noise in a processor and particularly to reducing power grid noise in a processor while minimizing performance loss.
In high performance processors, or other integrated circuits (ICs), to increase the processing performance of the processor, the processor chip design typically includes one or more of one or more processor cores and one or more pipelines connecting the processor cores. In addition, in a high performance system, processor system designs often include multiple chips sharing a common supply rail of a power distribution network providing a supply voltage. As the number of processor cores on a same chip or across multiple chips, all sharing a common supply rail, increases, the number of circuits that switch per clock cycle also increases.
In a processor there is noise generated by circuit switching activity at each clock cycle by nodes, busses, and other circuit components sharing a common supply rail. One result of noise generated by circuit switching activity, also referred to as power grid noise or di/dt noise, is that a sudden increase in noise will induce a droop in the supply voltage to the common supply rail of the power distribution network. A sudden, large droop in the supply voltage slows down the circuit response and therefore could cause timing errors on the logical circuit.
To reduce the noise generated by circuit switching activity, a processor may include decoupling capacitors positioned near the switching circuits of the processor cores, where the decoupling capacitors act as a charge reservoir and help reduce noise on the power distribution network as circuit switching activity increases. The supply voltage droop ΔV induced by an increase in circuit switching activity at the chip level is proportional to ΔI*square root(L/C), where ΔI is the increase in current required by chip level switching circuits on the common supply rail, L is the inductance from the chip level circuits to printed-circuit-board or package level, and C is the summed, chip level capacitance of the circuits on the common supply rail. Since many cores can be activated simultaneously, one limitation of implementing decoupling capacitors to reduce noise is in the case where there is a sudden burst of activity on one or more processor cores, increasing the current, and because ΔI is directly proportional to the number of cores on the common supply rail, the sudden increase in ΔI outweighs the noise reduction by the charge reservoirs of the decoupling capacitors, triggering a voltage droop.
To address this problem US 2014/0157277 A1 proposes a method for managing a processor comprising monitoring for an increase in logical operation activity from a low level to a high level during a sampling window across a plurality of cores sharing a common supply rail of the processor, responsive to the processor detecting the increase in logical operation activity from the low level to the high level during the sampling window, limiting the logical operations executed on the plurality of cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level; responsive to the lower activity period ending, gradually decreasing the limit on the logical operations executed on the plurality of cores to resume normal operations. The known method may not detect all logical operation activities which may lead to a voltage droop.